This application claims benefit and priority of Korean Patent Application No. 2001-19305, filed on Apr. 11, 2001, the contents of which are incorporated herein by reference in its entirety.
The present invention generally relates to a semiconductor device and its method of fabrication and, more specifically, to a ferroelectric memory having ferroelectric capacitors and its method of fabrication.
A ferroelectric memory is a type of nonvolatile memory that is able to keep previously stored data when power is lost. Furthermore, the ferroelectric memory device can operate at low voltage similarly to DRAM and SRAM. Because of these characteristics, ferroelectric memory devices are being more widely used in smart card applications.
FIG. 1 is a cross-sectional view illustrating a portion of a conventional ferroelectric memory device.
Referring to FIG. 1, a lower interlayer insulating layer 3 is deposited on semiconductor substrate 1. A predetermined region of semiconductor substrate 1 is in contact with contact plug 5, which passes through a predetermined region of the lower interlayer insulating layer 3. A lower electrode 7, which is in contact with an upper surface of contact plug 5, is located on the lower interlayer insulating layer 3. A ferroelectric layer 9 and upper electrode 11 are stacked over the lower electrode 7. A PZT (PbZrTiO3) or BST (BaSrTiO3) are commonly used for the ferroelectric material of layer 9. The stack of lower electrode 7, ferroelectric layer 9 and upper electrode 11 forms a ferroelectric capacitor. In addition, upper insulating layer 13 can be deposited over the ferroelectric capacitor and the lower interlayer insulating layer 3. Here, the lower interlayer insulating layer 3 and the upper insulating layer 13 may comprise, e.g., silicon oxide.
As described above, according to an exemplary known device, a sidewall of the ferroelectric layer 9 is directly exposed and in contact with subsequently formed insulating layer 13 such as, e.g., silicon oxide. Accordingly, during possible processes such as, e.g., a plasma process, a characteristic of the ferroelectric can be deteriorated. In other words, hydrogen ions of a plasma process might penetrate and damage the ferroelectric layer. If the hydrogen ions reach the ferroelectric, a chemical reduction reaction may occur, in which the hydrogen ions may react with oxygen atoms of the ferroelectric to generate oxygen vacancies. Thus, a crystalline structure of the ferroelectric layer is destroyed and a polarization characteristic deteriorated.
Additionally, if hydrogen ions are captured or trapped at the interface between the ferroelectric and the upper or lower electrodes, an energy barrier or level therebetween is lowered. Accordingly, with a reduced barrier energy, a leakage current characteristic of the ferroelectric capacitor is degraded.
In accordance with an exemplary embodiment of the present invention, a ferroelectric memory comprises a hydrogen barrier on a sidewall of a ferroelectric layer disposed between two electrodes.
In accordance with another exemplary embodiment of the present invention, a method of fabricating a ferroelectric memory comprises protecting ferroelectric material from hydrogen ions.
In accordance with a particular exemplary embodiment, a ferroelectric memory comprises a lower electrode over a semiconductor substrate. A ferroelectric layer is disposed over the lower electrode. A first portion of an upper electrode may be disposed over the ferroelectric layer and an insulating spacer disposed in contact with a sidewall of the lower electrode. A second portion of the upper electrode may cover a sidewall of the insulating spacer and contact at least part of the first portion of the upper electrode. The second portion of the upper electrode may be electrically insulated from the lower electrode by the insulating spacer, and electrically connected to the first portion of the upper electrode. In accordance with a further embodiment, insulating spacer may also cover a sidewall of the ferroelectric layer.
In accordance with another embodiment, the first and the second portion of the upper electrode may comprise a hydrogen barrier layer. In further embodiments the hydrogen barrier layer may comprise an iridium layer (Ir), an iridium oxide layer (IrO2) or a combination thereof.
In accordance with another exemplary embodiment, a method of fabricating a ferroelectric memory comprises forming a stack of a lower electrode, a ferroelectric layer and a first portion of an upper electrode over a substrate. An insulating spacer is formed against a sidewall of the lower electrode. In accordance with an optional aspect, the insulating spacer may be formed to also cover a sidewall of the ferroelectric layer as well as the sidewall of the lower electrode. Continuing the exemplary embodiment, a second portion for the upper electrode may be formed to cover a sidewall of the insulating spacer and at least a portion of the first portion of the upper electrode.
In accordance with further exemplary embodiments, the first portion of the upper electrode may be formed with a hydrogen barrier layer. In such embodiments, the hydrogen barrier layer may be formed of an iridium layer (Ir), an iridium oxide layer (IrO2) or a combination thereof.
In a further exemplary embodiment, the insulating spacer may be formed by depositing an insulating layer such as an oxide layer over the substrate and over the patterned stack of the lower electrode, the ferroelectric layer and the first portion of the upper electrode. The deposited insulating layer might then be anisotropically etched to expose at least a part of the first portion of the upper electrode.
In accordance with another exemplary embodiment, the second portion of the upper electrode may be formed by depositing a hydrogen barrier layer over the substrate and the insulating spacer, and then anisotropically etching the hydrogen barrier layer.